The present invention relates in general to semiconductor devices for use in integrated circuits (ICs). More specifically, the present invention relates to improved fabrication methodologies and resulting structures for a low-power random number generator that uses a thin-film transistor (TFT).
Metal oxide semiconductor field effect transistors (MOSFETs) include a source and a drain that are formed in the active region of a semiconductor layer by implanting n-type or p-type impurities in the semiconductor layer. A conventional geometry for MOSTFETs is known as a “planar” geometry because the various parts of the MOSFET device are laid down as planes or layers.
A TFT is a type of FET that can be fabricated by depositing thin films of an active semiconductor layer, dielectric layers, metallic gates, and metallic contacts. A “thin-film” layer's thickness can range from fractions of a nanometer to several micrometers. Faster TFTs can be achieved by using, for example, low temperature polycrystalline silicon (LTPS) or transparent semiconducting oxides (TSOs), thereby potentially expanding TFT application to gate and data drivers or even full systems-on-panel. TFTs can be formed on bulk semiconductor substrates or on semiconductor-on-insulator (SOI) substrates. When bulk semiconductors are used, isolation is provided by implanted wells filled with shallow trench isolation (STI) regions that separate one TFT from another. When SOI is used, TFTs are formed in the semiconductor layer, and no wells are needed because of the isolating material that is already present in the SOI substrate. For liquid-crystal display (LCD) applications, a common non-conductive TFT SOI insulator is glass. This differs from the conventional MOSFET, wherein the insulator of an SOI substrate is typically a dielectric material such as an oxide.